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ltc4253/ltc4253a 1 425353afe C 48v/2.5a hot swap controller start-up behavior typical application features description ?48v hot swap controllers with sequencer the ltc ? 4253/ltc4253a negative voltage hot swap? controllers allow a board to be safely inserted and removed from a live backplane. output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault condi- tions. the ltc4253/ltc4253a latch off after a circuit fault. adjustable undervoltage and overvoltage detectors dis- connect the load whenever the input supply exceeds the desired operating range. the ltc4253/ltc4253as supply input is shunt-regulated, allowing safe operation with very high supply voltages. a multifunction timer delays initial start-up and controls the circuit breakers response time. the circuit breakers response time can be accelerated by sensing excessive mosfet drain voltage, keeping the mosfet within its safe operating area (soa). an adjustable soft-start circuit controls mosfet inrush current at start-up. three power good outputs are sequenced by an adjustable timer and two enable inputs to enable external power modules at start-up or disable them if the circuit breaker trips. the ltc4253a features tight 1% undervoltage/ overvoltage threshold accuracy. the ltc4253/ltc4253a are available in a 16-pin ssop . applications n allows safe board insertion and removal from a live C48v backplane n floating topology permits very high voltage operation n adjustable analog current limit with breaker timer ideal for two battery feeds n fast response time limits peak fault current n adjustable undervoltage/overvoltage protection with 1% threshold accuracy (ltc4253a) n three sequenced power good outputs n adjustable soft-start current limit n adjustable timer with drain voltage accelerated response n latchoff after fault n available in a 16-pin ssop package n C48v distributed power systems n negative power supply control n central office switching n high availability servers n disk arrays l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 5.6k 5.6k 5.6k ? pwrgd1 v in en2 en3 v in v ee ltc4253 load1 pwrgd2 pwrgd3 ov drain ss gate sqtimer sense timer en load2 en load3 en 2.5k 15k(1/4w)/6 uv reset 4253 ta01 10 1m 0.02 irf530s *diodes, inc. ? moc207 ?? recommended for harsh environments. 18nf 0.33f 0.1f 68nf 10nf + 100f b3100* 402k 1% C 48v a C 48v b C 48v rtn C 48v rtn b3100* ? ? 32.4k 1% 1f d in ?? ddz13b* gate 10v ss 1v sense 50mv v out 50v 1ms/div 4253 ta01b not recommended for new designs please see ltc4253b for drop-in replacement
ltc4253/ltc4253a 2 425353afe pin configuration absolute maximum ratings current into v in (100s pulse) .............................100ma current into drain (100s pulse) .........................20ma v in , drain minimum voltage ................................C0.3v input/output (except sense and drain) voltage ................................... C0.3v to 16v sense voltage ........................................... C0.6v to 16v current out of sense (20s pulse) .................. C200ma maximum junction temperature .......................... 125c operating temperature range ltc4253c ................................................ 0c to 70c ltc4253i ............................................. C40c to 85c ltc4253ac (obsolete) ......................... 0c to 70c ltc4253ai (obsolete) ...................... C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c (note 1), all voltages referred to v ee 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 en2 pwrgd2 pwrgd1 v in reset ss sense v ee pwrgd3 en3 sqtimer timer uv ov drain gate t jmax = 125c, ja = 130c/w order information lead free finish tape and reel part marking package description temperature range ltc4253cgn#pbf ltc4253cgn#trpbf 4253 16-lead plastic ssop 0c to 70c ltc4253ign#pbf ltc4253ign#trpbf 4253i 16-lead plastic ssop C40c to 85c obsolete package ltc4253acgn#pbf ltc4253acgn#trpbf 4253a 16-lead plastic ssop 0c to 70c ltc4253aign#pbf ltc4253aign#trpbf 4253ai 16-lead plastic ssop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4253/ltc4253a 3 425353afe electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 2) symbol parameter conditions ltc4253 ltc4253a units min typ max min typ max v z v in C v ee zener voltage i in = 2ma 11.5 13 14.5 11.5 13 14.5 v r z v in C v ee zener dynamic impedance i in = (2ma to 30ma) 5 5 i in v in supply current uv = ov = 4v, v in = (v z C 0.3v) 0.8 2 1.1 2 ma v lko v in undervoltage lockout coming out of uvlo (rising v in ) 9.2 11.5 9 10 v v lkh v in undervoltage lockout hysteresis 0.5 1 1.5 0.25 0.5 0.75 v v ih ttl input high voltage 22 v v il ttl input low voltage 0.8 0.8 v v hyst ttl input buffer hysteresis 600 600 mv i reset reset input current v ee v reset v in 0.1 10 0.1 10 a i en en2, en3 input current v en = 4v v en = 0v 60 120 0.1 180 10 60 120 0.1 180 10 a a v cb circuit breaker current limit voltage v cb = (v sense C v ee ) 40 50 60 45 50 55 mv v acl analog current limit voltage v acl = (v sense C v ee ), ss = open or 2.2v 80 100 120 mv v acl v cb analog current limit voltage circuit breaker current limit voltage v acl = (v sense C v ee ), ss = open or 1.4v 1.05 1.20 1.38 v/v v fcl fast current limit voltage v fcl = (v sense C v ee ) 150 200 300 150 200 300 mv v ss ss voltage after end of ss timing cycle 2 2.2 2.4 1.25 1.4 1.55 v i ss ss pin current uv = ov = 4v, v sense = v ee, v ss = 0v (sourcing) 12 22 32 16 28 40 a uv = ov = 0v, v sense = v ee, v ss = 1v (sinking) 28 28 ma r ss ss output impedance 100 50 k v os analog current limit offset voltage 10 10 mv v acl + v os v ss ratio (v acl + v os ) to ss voltage 0.05 0.05 v/v i gate gate pin output current uv = ov = 4v, v sense = v ee , v gate = 0v (sourcing) 30 50 70 30 50 70 a uv = ov = 4v, v sense C v ee = 0.15v, v gate = 3v (sinking) 17 17 ma uv = ov = 4v, v sense C v ee = 0.3v, v gate = 1v (sinking) 190 190 ma v gate external mosfet gate drive v gate C v ee, i in = 2ma 10 12 v z 10 12 v z v v gatel gate low threshold before gate ramp up 0.5 0.5 v v gateh gate high threshold v gateh = v in C v gate , for pwrgd1 , pwrgd2 , pwrgd3 status 2.8 2.8 v v uvhi uv pin threshold high uv low to high 3.075 3.225 3.375 v v uvlo uv pin threshold low uv high to low 2.775 2.925 3.075 v v uv uv pin threshold uv low to high 3.05 3.08 3.11 v v uvhst uv pin hysteresis 230 300 350 292 324 356 mv mv v ovhi ov pin threshold high ov low to high 5.85 6.15 6.45 v v ovlo ov pin threshold low ov high to low 5.55 5.85 6.15 v
ltc4253/ltc4253a 4 425353afe electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions ltc4253 ltc4253a units min typ max min typ max v ov ov pin threshold ov low to high 5.04 5.09 5.14 v v ovhst ov pin hysteresis 230 300 350 82 102 122 mv mv i sense sense pin input current uv = 0v = 4v, v sense = 50mv (sourcing) 15 30 15 30 a i inp uv, ov pin input current uv = ov = 4v 0.1 1 0.1 1 a v tmrh timer pin voltage high threshold 3.5 4 4.5 3.5 4 4.5 v v tmrl timer pin voltage low threshold 0.8 1 1.2 0.8 1 1.2 v i tmr timer pin current timer on (initial cycle/latchoff, sourcing), v tmr = 2v 357357 a timer off (initial cycle, sinking), v tmr = 2v 28 28 ma timer on (circuit breaker, sourcing, i drn = 0a), v tmr = 2v 120 200 280 120 200 280 a timer on (circuit breaker, sourcing, i drn = 50a), v tmr = 2v 600 600 a timer off (circuit breaker, sinking), v tmr = 2v 357357 a i tmracc i drn i tmr at i drn = 50a C i tmr at i drn = 0a 50a timer on (circuit breaker with i drn = 50a) 789789a/a v sqtmrh sqtimer pin voltage high threshold 3.5 4 4.5 3.5 4 4.5 v v sqtmrl sqtimer pin voltage low threshold 0.33 0.33 v i sqtmr sqtimer pin current sqtimer on (power good sequence, sourcing), v sqtmr = 2v 357357 a sqtimer off (power good sequence, sinking), v sqtmr = 2v 28 28 ma v drnl drain pin voltage low threshold for pwrgd1 , pwrgd2 , pwrgd3 status 2 2.39 3 2 2.39 3 v i drnl drain leakage current v drain = 5v v drain = 4v 0.1 1 0.1 1 a a v drncl drain pin clamp voltage i drn = 50a 678.5567.5 v v pgl pwrgd1 , pwrgd2 , pwrgd3 output low voltage i pg = 1.6ma i pg = 5ma 0.25 0.4 1.2 0.25 0.4 1.2 v v i pgh pwrgd1 , pwrgd2 , pwrgd3 output high current v pg = 0v (sourcing) 30 50 70 30 50 70 a t sq sqtimer default ramp period sqtimer pin floating, v sqtmr ramps from 0.5v to 3.5v 250 250 s t ss ss default ramp period ss pin floating, v ss ramps from 0.2v to 2v ss pin floating, v ss ramps from 0.2v to 1.25v 250 140 s s t pllug uv low to gate low 0.4 5 0.4 5 s t phlog ov high to gate low 0.4 5 0.4 5 s note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise specified.
ltc4253/ltc4253a 5 425353afe typical performance characteristics i en vs v en circuit breaker current limit voltage v cb vs temperature analog current limit voltage v acl vs temperature fast current limit voltage v fcl vs temperature i gate (source) vs temperature i gate (acl, sink) vs temperature v z vs temperature i in vs v in i in vs temperature temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v z (v) 4253 g01 14.5 14.0 13.5 13.0 12.5 12.0 i in = 2ma v in (v) 0 5 10 15 20 i in (ma) 4253 g02 1000 100 10 1 0.1 t a = 85c t a = 125c t a = C40c t a = 25c temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i in (a) 4253 g03 1000 950 900 850 800 750 700 650 600 550 500 v in = v z C 0.3v v en (v) 02 4 6 8 10 12 14 16 i en (a) 4253 g04 180 160 140 120 100 80 60 40 20 0 i in = 2ma t a = 25c temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v cb (mv) 4253 g05 55 54 53 52 51 50 49 48 47 46 45 temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v acl (mv) 4253 g06 150 140 130 120 110 100 90 80 70 60 50 temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v fcl (mv) 4253 g07 300 280 260 240 220 200 180 160 140 120 100 temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i gate (a) 4253 g08 60 58 56 54 52 50 48 46 44 42 40 uv/ov = 4v timer = 0v v sense = v ee v gate = 0v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i gate (ma) 4253 g09 30 25 20 15 10 5 0 uv/ov = 4v timer = 0v v sense C v ee = 0.15v v gate = 3v
ltc4253/ltc4253a 6 425353afe typical performance characteristics v gateh vs temperature uv threshold vs temperature ov threshold vs temperature i sense vs (v sense C v ee )i sense vs temperature timer threshold vs temperature i gate (fcl, sink) vs temperature v gate vs temperature v gatel vs temperature temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i gate (ma) 4253 g10 400 350 300 250 200 150 100 50 0 uv/ov = 4v timer = 0v v sense C v ee = 0.3v v gate = 1v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v gateh (v) 4253 g13 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 uv/ov = 4v v gateh = v in C v gate i in = 2ma v sense C v ee (v) C1.5 C1 C0.5 0 0.5 1 1.5 Ci sense (ma) 4253 g16 0.01 0.1 1 10 100 1000 uv/ov = 4v timer = 0v gate = high t a = 25c temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v gate (v) 4253 g11 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 uv/ov = 4v timer = 0v v sense = v ee i in = 2ma temperature (c) C55 C35 C15 5 25 45 65 85 105 125 uv threshold (v) 4253 g14 3.375 3.275 3.175 3.075 2.975 2.875 2.775 i in = 2ma v uvh v uvl v uv temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i sense (a) 4253 g17 0 C5 C10 C15 C20 C25 C30 uv/ov = 4v timer = 0v v sense C v ee = 50mv v gate = high temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v gatel (v) 4253 g12 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 uv/ov = 4v timer = 0v gate threshold before ramp up temperature (c) C55 C35 5.0 ov threshold (v) 5.4 5.6 5.8 65 85 105 6.4 4352 g15 5.2 C15 525 45 125 6.0 6.2 v ovh i in = 2ma v ovl v ov temperature (c) C55 C35 C15 5 25 45 65 85 105 125 timer threshold (v) 4253 g18 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 i in = 2ma v tmrh v tmrl
ltc4253/ltc4253a 7 425353afe typical performance characteristics i tmracc /i drn vs temperature sqtimer threshold vs temperature v drnl vs temperature v drncl vs temperature i drn vs v drain v pgl vs temperature i tmr (initial cycle, sourcing) vs temperature i tmr (circuit breaker, sourcing) vs temperature i tmr vs i drn temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i tmr (a) 4253 g19 10 9 8 7 6 5 4 3 2 1 0 i in = 2ma v tmr = 2v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i tmracc /i drn (a/a) 4253 g22 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 i in = 2ma temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v drncl (v) 4253 g25 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 i in = 2ma i drn = 50a temperature (c) C55 C35 C15 5 25 45 65 85 105 125 i tmr (a) 4253 g20 240 230 220 210 200 190 180 170 160 i in = 2ma i drn = 0a temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v sqtmr (v) 4253 g23 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 i in = 2ma v sqtmrh v sqtmrl v drain (v) 0 2 4 6 8 10 12 14 16 i drn (ma) 4253 g26 100 10 1 0.1 0.01 0.001 0.0001 0.00001 i in = 2ma t a = C40c t a = 25c t a = 85c t a = 125c i drn (ma) 0.001 0.01 0.1 110 i tmr (ma) 4253 g21 10 1 0.1 i in = 2ma t a = 25c temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v drnl (v) 4253 g24 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 i in = 2ma temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v pgl (v) 4253 g27 3.0 2.5 2.0 1.5 1.0 0.5 0 i in = 2ma i pg = 10ma i pg = 5ma i pg = 1.6ma
ltc4253/ltc4253a 8 425353afe typical performance characteristics i pgh vs temperature t ss vs temperature t sq vs temperature temperature (c) C55 C35 C15 5 25 45 65 85 105 125 v pgh (a) 4253 g28 60 58 56 54 52 50 48 46 44 42 40 i in = 2ma v pwrgd = 0v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 t ss (s) 4253 g29 300 290 280 270 260 250 240 230 220 210 200 i in = 2ma ss pin floating v ss ramps from 0.2v to 2v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 t sq (s) 4253 g30 500 450 400 350 300 250 200 150 100 50 0 i in = 2ma v sqtmr ramps from 0.5v to 3.5v en2 (pin 1): power good status output two enable. this is a ttl compatible input that is used to control pwrgd2 and pwrgd3 outputs. when en2 is driven low, both pwrgd2 and pwrgd3 will go high. when en2 is driven high, pwrgd2 will go low provided pwrgd1 has been active for more than one power good sequence delay (t sqt ) provided by the sequencing timer. en2 can be used to control the power good sequence. this pin is internally pulled low by a 120a current source. pwrgd2 (pin 2): power good status output two. power good sequence starts with pwrgd1 latching active low. pwrgd2 will latch active low after en2 goes high and after one power good sequence delay t sqt provided by the sequencing timer from the time pwrgd1 goes low, whichever comes later. pwrgd2 is reset by pwrgd1 going high or en2 going low. this pin is internally pulled high by a 50a current source. pwrgd1 (pin 3): power good status output one. at start- up, pwrgd1 latches active low and starts the power good sequence when the drain pin is below 2.39v and gate is within 2.8v of v in . pwrgd1 status is reset by uv, v in (uvlo), reset going high or circuit breaker fault time-out. this pin is internally pulled high by a 50a current source. v in (pin 4): positive supply input. connect this pin to the positive side of the supply through a dropping resistor. a shunt regulator clamps v in at 13v above v ee . an internal undervoltage lockout (uvlo) circuit holds gate low until the v in pin is greater than v lko , overriding uv and ov. if uv is high, ov is low and v in comes out of uvlo, timer starts an initial timing cycle before initiating gate ramp up. if v in drops below approximately 8.2v (8.5v for the ltc4253a), gate pulls low immediately. reset (pin 5): circuit breaker reset pin. this is an asyn- chronous ttl compatible input. reset going high will pull gate, ss, timer, sqtimer low and the pwrgd outputs high. the reset pulse must be wide enough to discharge any voltage on the timer pin below v tmrl . after the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in interlock conditions in the operation section. ss (pin 6): soft-start pin. this pin is used to ramp inrush current during start up, thereby effecting control over di/dt. a 20x attenuated version of the ss pin voltage is presented to the current limit amplifier. this attenuated voltage limits the mosfets drain current through the sense resistor during the soft-start current limiting. at the beginning of pin functions
ltc4253/ltc4253a 9 425353afe the start-up cycle, the ss capacitor (c ss ) is ramped by a 22a (28a for the ltc4253a) current source. the gate pin is held low until ss exceeds 20 ? v os = 0.2v. ss is internally shunted by a 100k r ss which limits the ss pin voltage to 2.2v (50k resistor and 1.4v for the ltc4253a). this corresponds to an analog current limit sense voltage of 100mv (60mv for the ltc4253a). if the ss capacitor is omitted, the ss pin ramps up in about 250s (140s for the ltc4253a). the ss pin is pulled low under any of the following conditions: uvlo at v in , uv, ov, during the initial timing cycle, a circuit breaker fault time-out or the reset pin going high. sense (pin 7): circuit breaker/current limit sense pin. load current is monitored by a sense resistor r s connected between sense and v ee , and controlled in three steps. if sense exceeds v cb (50mv), the circuit breaker compara- tor activates a (200a?+?8???i drn ) timer pull-up current. if sense exceeds v acl , the analog current-limit amplifier pulls gate down to regulate the mosfet current at v acl / r s . in the event of a catastrophic short-circuit, sense may overshoot v acl . if sense reaches v fcl (200mv), the fast current-limit comparator pulls gate low with a strong pull-down. to disable the circuit breaker and current limit functions, connect sense to v ee . v ee (pin 8): negative supply voltage input. connect this pin to the negative side of the power supply. gate (pin 9): n-channel mosfet gate drive output. this pin is pulled high by a 50a current source. gate is pulled low by invalid conditions at v in (uvlo), uv, ov, during the initial timing cycle, a circuit breaker fault time-out or the reset pin going high. gate is actively servoed to control the fault current as measured at sense. compensation capacitor, c c , at gate stabilizes this loop. a comparator monitors gate to ensure that it is low before allowing an initial timing cycle, then the gate ramps up after an over- voltage event or restart after a current limit fault. during gate start-up, a second comparator detects gate within 2.8v of v in before pwrgd1 can be set and power good sequencing starts. drain (pin 10): drain sense input. connecting an external resistor, r d between this pin and the mosfets drain (v out ) allows voltage sensing below 6.15v (5v for ltc4253a) and current feedback to timer. a comparator detects if drain is below 2.39v and together with the gate high comparator, sets the pwrgd1 flag. if v out is above v drncl , the drain pin is clamped at approximately v drncl . r d current is internally multiplied by 8 and added to timers 200a during a circuit breaker fault cycle. this reduces the fault time and mosfet heating. ov (pin 11): overvoltage input. for the ltc4253, the threshold at the ov pin is set at 6.15v with 0.3v hys- teresis. if ov > 6.15v, gate pulls low. when ov returns below 5.85v, gate start-up begins without an initial timing cycle. the ltc4253a ov threshold is set at 5.09v with 102mv hysteresis. if ov > 5.09v, gate pulls low. when ov returns below 4.988v, gate start-up begins without an initial timing cycle. if ov occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after ov goes away. ov does not reset the latched fault or pwrgd1 flag. the internal uvlo at v in always overrides ov. a 1nf to 10nf capacitor at ov prevents transients and switch- ing noise from affecting the ov thresholds and prevents glitches at the gate. uv (pin 12): undervoltage input. for the ltc4253, the threshold at the uv pin is set at 3.225v with 0.3v hysteresis. if uv < 2.925v, pwrgd1 pulls high, both gate and timer pull low. if uv rises above 3.225v, this initiates an initial timing cycle followed by gate start-up. the ltc4253a uv threshold is set at 3.08v with 324mv hysteresis. if uv < 2.756v, pwrgd1 pulls high, both gate and timer pull low. if uv rises above 3.08v, this initiates an initial timing cycle followed by gate start-up. the internal uvlo at v in always overrides uv. a low at uv resets an internal fault latch. a 1nf to 10nf capacitor at uv prevents transients and switching noise from affecting the uv thresholds and prevents glitches at the gate pin. pin functions
ltc4253/ltc4253a 10 425353afe pin functions timer (pin 13): timer input. timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). timer starts an initial timing cycle when the following conditions are met: reset is low, uv is high, ov is low, v in clears uvlo, timer pin is low, gate pin is lower than v gatel , ss < 0.2v, and v sense C v ee < v cb . a pull-up current of 5a then charges c t , generating a time delay. if c t charges to v tmrh (4v), the timing cycle terminates. timer quickly pulls low and gate is activated. if sense exceeds 50mv while gate is high, a circuit breaker cycle begins with a 200a pull-up current charging c t . if drain is approximately 7v (6v for the ltc4253a) dur- ing this cycle, the timer pull-up has an additional current of 8 ? i drn . if sense drops below 50mv before timer reaches 4v, a 5a pull-down current slowly discharges the c t . in the event that c t eventually integrates up to the v tmrh (4v) threshold, the circuit breaker trips, gate quickly pulls low and pwrgd1 pulls high. timer latches high with a 5a pull-up source. this latched fault may be cleared by driving reset high until timer is pulled low. other ways of clearing the fault include pulling the v in pin momentarily below (v lko C v lkh ), pulling timer low with an external device or pulling uv below 2.925v (2.756v for the ltc4253a). sqtimer (pin 14): sequencing timer input. the sequenc- ing timer provides a delay t sqt for the power good sequenc- ing. this delay is adjusted by connecting an appropriate capacitor to this pin. if the sqtimer capacitor is omitted, the sqtimer pin ramps from 0v to 4v in about 300s. en3 (pin 15): power good status output three enable. this is a ttl compatible input that is used to control the pwrgd3 output. when en3 is driven low, pwrgd3 will go high. when en3 is driven high, pwrgd3 will go low provided pwrgd2 has been active for for more than one power good sequence delay (t sqt ). en3 can be used to control the power good sequence. this pin is internally pulled low by a 120a current source. pwrgd3 (pin 16): power good status output three. power good sequence starts with pwrgd1 latching active low. pwrgd3 will latch active low after en3 goes high and after one power good sequence delay t sqt provided by the sequencing timer from the time pwrgd2 goes low, whichever comes later. pwrgd3 is reset by pwrgd1 going high or en3 going low. this pin is internally pulled high by a 50a current source.
ltc4253/ltc4253a 11 425353afe block diagram v ee 1 6.15v (5v) 1 8 1 v in v ee pwrgd3 50a 6.15v (5.09v) v ee 120a v ee 120a v in v in v ee v in v ee 200a 16 ov 11 en3 15 v in v ee v ee 22a (28a) for components, currents and voltages with two values, values without parentheses refer to the ltc4253, values with parentheses refer to the ltc4253a 95k (47.5k) r ss 5k (2.5k) ss 6 v in v in v ee v ee 50a v in v in v ee pwrgd2 50a 2 en2 1 v ee pwrgd1 50a 3 4 v ee 8 reset 5 sqtimer delay logic sqtimer delay + C 4v + C 1v timer 13 + C 4v + C 0.33v + C uv 12 2.925v (2.756v) + C + C 0.5v + C 2.39v + C C + v in v ee 5a v in v ee 5a 5a + C 2.8v + C 200mv + C 10mv v ee C + + C 50mv 4253 bd cb fcl C + acl v ee sense 7 gate 9 drain 10 sqtimer 14
ltc4253/ltc4253a 12 425353afe operation hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. the flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. the ltc4253/ltc4253a are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. initial start-up the ltc4253/ltc4253a reside on a removable circuit board and control the path between the connector and load or power conversion circuitry with an external mosfet switch (see figure 1). both inrush control and short-circuit protection are provided by the mosfet. a detailed schematic is shown in figure 2. C 48v and C48rtn receive power through the longest connector pins and are the first to connect when the board is inserted. the gate pin holds the mosfet off during this time. uv/ ov determines whether or not the mosfet should be turned on based upon internal high accuracy thresholds and an external divider. uv/ov does double duty by also monitoring whether or not the connector is seated. the top of the divider detects C48rtn by way of a short connector pin that is the last to mate during the insertion sequence. figure 2. C48v/2.5a application with a wider operating range figure 1. basic ltc4253/ltc4253a hot swap topology ltc4253 ltc4253a C48rtn 4253 f01 plug-in board C48v backplane + c load isolated dc/dc converter module low voltage circuitry + C + C r5 5.6k r4 5.6k r6 5.6k pwrgd1 v in v ee ltc4253 power module 1 pwrgd2 pwrgd3 en3 en2 uv ov reset drain ss gate sqtimer sense timer en power module 2 en power module 3 en r in 2.5k 15k(1/4w)/6 push reset en3 4253 f02 en2 r c 10 r d 1m r s 0.02 q1 irf530s v in c c 18nf c t 0.33f c1 10nf C48rtn (long pin) C48rtn (short pin) C48v (long pin) c sq 0.1f c ss 68nf r7 power module 1 output power module 2 output v in r8 + c l 100f c in 1f d in ?? ddz13b* r1 38.3k 1% r3 432k 1% r9 47k r2 4.75k 1% ??? ? ? *diodes, inc. ? moc207 ?? recommended for harsh environments. v in
ltc4253/ltc4253a 13 425353afe operation interlock conditions a start-up sequence commences once these interlock conditions are met: 1. the input voltage v in exceeds v lko (uvlo). 2. the voltage at uv > v uvhi (v uv for the ltc4253a). 3. the voltage at ov < v ovlo (v ov C v ovhst for the ltc4253a). 4. the input voltage at reset < 0.8v. 5. the (sense C v ee ) voltage < 50mv (v cb ) 6. the voltage at ss is < 0.2v (20 ? v os ) 7. the voltage on the timer capacitor (c t ) is < 1v (v tmrl ). 8. the voltage at gate is < 0.5v (v gatel ) the first four conditions are continuously monitored and the latter four are checked prior to initial timing or gate ramp-up. upon exiting an ov condition, the timer pin voltage requirement is inhibited. details are described in the applications information, timing waveforms section. if reset < 0.8v occurs after the ltc4253/ltc4253a come out of uvlo (interlock condition 1) and undervoltage (in- terlock condition 2), gate and ss are released without an initial timer cycle once the other interlock conditions are met (see figure 13a). if not, timer begins the start-up sequence by sourcing 5a into c t . if v in , uv or ov falls out of range or reset asserts, the start-up cycle stops and timer discharges c t to less than 1v, then waits until the aforementioned conditions are once again met. if c t successfully charges to 4v, timer pulls low and both ss and gate pins are released. gate sources 50a (i gate ), charging the mosfet gate and associated capacitance. the ss voltage ramp limits v sense to control the inrush current. pwrgd1 pulls active low when gate is within 2.8v of v in and drain is lower than v drnl . this sets off the power good sequence in which pwrgd2 and then pwrgd3 is subsequently pulled low after a delay, adjust- able through the sqtimer capacitor c sq or by external control inputs en2 and en3. in this way, external loads or power modules controlled by the three pwrgd signals are turned on in a controlled manner without overloading the power bus. two modes of operation are possible during the time the mosfet is first turned on, depending on the values of external components, mosfet characteristics and nominal design current. one possibility is that the mosfet will turn on gradually so that the inrush into the load capaci- tance remains a low value. the output will simply ramp to C48v and the ltc4253/ltc4253a will fully enhance the mosfet. a second possibility is that the load current exceeds the soft-start current limit threshold of [v ss (t)/ 20 C v os ]/r s . in this case the ltc4253/ltc4253a ramp the output by sourcing soft-start limited current into the load capacitance. if the soft-start voltage is below 1.2v, the circuit breaker timer is held low. above 1.2v, timer ramps up. it is important to set the timer delay so that, regardless of which start-up mode is used, the timer ramp is less than one circuit breaker delay time. if this condition is not met, the ltc4253/ltc4253a may shut down after one circuit breaker delay time. board removal when the board is withdrawn from the card cage, the uv/ ov divider is the first to lose connection. this shuts off the mosfet and commutates the flow of current in the connector. when the power pins subsequently separate there is no arcing. current control three levels of protection handle short-circuit and over- load conditions. load current is monitored by sense and resistor r s . there are three distinct thresholds at sense: 50mv for a timed circuit breaker function; 100mv for an analog current limit loop (60mv for the ltc4253a); and 200mv for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. if, due to an output overload, the voltage drop across r s exceeds 50mv, timer sources 200a into c t . c t eventually charges to a 4v threshold and the ltc4253/ltc4253a shut off. if the overload goes away before c t reaches 4v and sense measures less than 50mv, c t slowly discharges (5a). in this way the ltc4253/ltc4253as circuit breaker function responds to low duty cycle overloads, and ac- counts for the fast heating and slow cooling characteristic of the mosfet.
ltc4253/ltc4253a 14 425353afe applications information operation higher overloads are handled by an analog current limit loop. if the drop across r s reaches v acl , the current limiting loop servos the mosfet gate and maintains a constant output current of v acl /r s . in current limit mode, v out (mosfet drain-source voltage drop) typically rises and this increases mosfet heating. if v out > v drncl , connecting an external resistor, r d between v out and drain allows the fault timing cycle to be shortened by accelerating the charging of the timer capacitor. the timer pull-up current is increased by 8 ? i drn . note that because sense > 50mv, timer charges c t during this time, and the ltc4253/ltc4253a eventually shut down. low impedance failures on the load side of the ltc4253/ ltc4253a, coupled with 48v or more driving potential, can produce current slew rates well in excess of 50a/s. under these conditions, overshoot is inevitable. a fast sense comparator with a threshold of 200mv detects overshoot and pulls gate low much harder and hence much faster than the weaker current limit loop. the v acl / r s current limit loop then takes over and servos the cur- rent as previously described. as before, timer runs and shuts down the ltc4253/ltc4253a when c t reaches 4v. if c t reaches 4v, the ltc4253/ltc4253a latch off with a 5a pull-up current source. the ltc4253/ltc4253a circuit breaker latch is reset by either pulling the reset pin active high until timer goes low, pulling uv momentarily low, dropping the input voltage v in below the internal uvlo threshold or pulsing timer momentarily low with a switch. although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. the action of timer and c t rejects these events allowing the ltc4253/ltc4253a to ride out temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse. pins, the area in and around the ltc4253 and all associ- ated components should be free of any other planes such as chassis ground, return, or secondary-side power and ground planes. v in may be biased with additional current up to 30ma, to accomodate external loading such as the pwrgd opto- couplers shown in figure 2. as an alternative to running higher current, simply buffer v in with an emitter follower as shown in figure 3. a method that cascodes the pwrgd outputs as shown in figure 17. v in is rated to handle 30ma within the thermal limits of the package, and is tested to survive a 100s, 100ma shunt regulator a fast responding shunt regulator clamps the v in pin to 13v (v z ). power is derived from C48rtn by an external current limiting resistor, r in . a 1f decoupling capacitor, c in filters supply transients and contributes a short delay at start-up. to meet creepage requirements r in may be split into two or more series connected units. this introduces a wider total spacing than is possible with a single component while at the same time ballasting the potential across the gap under each resistor. the ltc4253 is fundamentally a low voltage device that operates with C48v as its reference ground. to further protect against arc discharge into its
ltc4253/ltc4253a 15 425353afe applications information an ov hysteretic comparator detects overvoltage condi- tions at the ov pin, with the following thresholds: ov low-to-high (v ovhi ) = 6.150v ov high-to-low (v ovlo ) = 5.850v the uv and ov trip point ratio is designed to match the standard telecom operating range of 43v to 82v when connected together as in the typical application. a resistive divider is used to scale the supply voltage. using 402k and 32.4k gives a typical operating range of 43.2v to 82.5v. the undervoltage shutdown and overvoltage recovery thresholds are then 39.2v and 78.4v. 1% divider resistors are recommended to preserve threshold accuracy. the resistive divider values shown set a standing current of slightly more than 100a and define an impedance at uv/ov of 30k. in most applications, 30k impedance coupled with 300mv uv hysteresis make the ltc4253 insensitive to noise. if more noise immunity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . pulse. to protect v in against damage from higher am- plitude spikes, clamp v in to v ee with a 13v zener diode. star connect v ee and all v ee -referred components to the sense resistor kelvin terminal as illustrated in figure 3, keeping trace lengths between v in , c in , d in and v ee as short as possible. internal undervoltage lockout (uvlo) a hysteretic comparator, uvlo, monitors v in for undervolt- age. the thresholds are defined by v lko and its hysteresis v lkh . when v in rises above v lko , the chip is enabled; below (v lko C v lkh ), it is disabled and gate is pulled low. the uvlo function at v in should not be confused with the uv and ov pins. these are completely separate functions. uv/ov comparators (ltc4253) a uv hysteretic comparator detects undervoltage condi- tions at the uv pin, with the following thresholds: uv low-to-high (v uvhi ) = 3.225v uv high-to-low (v uvlo ) = 2.925v figure 3. C48v/2.5a application for the ltc4253a (refer to block diagram) r5 2.2k r4 2.2k r6 2.2k pwrgd1 v in v ee ltc4253a power module 1 pwrgd2 pwrgd3 en3 en2 uv ov reset drain ss gate sqtimer sense timer en power module 2 en power module 3 en r in 10k 20k(1/4w)/2 push reset en3 4253 f03 en2 r c 10 r d 1m r s 0.02 q1 irf530s q2 fzt857 v in1 c c 10nf c t 0.68f c1 10nf c sq 0.1f c ss 33nf r7 power module 1 output power module 2 output v in1 r8 + c l 100f c in 1f r1 30.1k 1% r2 392k 1% r9 47k r3 22k v in1 ??? ? ? C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin) d in ?? ddz13b* *diodes, inc. ? moc207 ?? recommended for harsh environments.
ltc4253/ltc4253a 16 425353afe applications information the separate uv and ov pins can be used for wider op- erating range such as 35.6v to 76.3v range as shown in figure 2. other combinations are possible with different resistors arrangement. uv/ov comparators (ltc4253a) a uv hysteretic comparator detects undervoltage condi- tions at the uv pin, with the following thresholds: uv low-to-high (v uv ) = 3.08v uv high-to-low (v uv C v uvhst ) = 2.756v an ov hysteretic comparator detects overvoltage condi- tions at the ov pin, with the following thresholds: ov low-to-high (v ov ) = 5.09v ov high-to-low (v ov C v ovhst ) = 4.988v the uv and ov trip point ratio is designed to match the standard telecom operating range of 43v to 71v when connected together as in figure 3. a divider (r1, r2) is used to scale the supply voltage. using r1 = 392k and r2 = 30.1k gives a typical operating range of 43.2v to 71.4v. the undervoltage shutdown and overvoltage recovery thresholds are then 38.6v and 69.9v. 1% divider resistors are recommended to preserve threshold accuracy. the r1-r2 divider values shown in figure 3 set a stand- ing current of slightly more than 100a and define an impedance at uv/ov of 28k. in most applications, 28k impedance coupled with 324mv uv hysteresis makes the ltc4253a insensitive to noise. if more noise im- munity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . the uv and ov pins can also be used for a wider operating range by adding a resistor between uv and ov as shown in figure 2 for the ltc4253. other combinations are pos- sible with different resistor arrangements. uv/ov operation a low input to the uv comparator will reset the chip and pull the gate and timer pins low. a low-to-high uv transition will initiate an initial timing sequence if the other interlock conditions are met. a high-to-low transition in the uv comparator immediately shuts down the ltc4253/ ltc4253a, pulls the mosfet gate low and resets the three latched pwrgd signals high. an overvoltage condition is detected by the ov compara- tor and pulls gate low, thereby shutting down the load, but it will not reset the circuit breaker timer and pwrgd flags. returning from the overvoltage condition will restart the gate pin if all the interlock conditions except timer are met. only during the initial timing cycle does ov condition have an effect of resetting timer. drain connecting an external resistor, r d , to this dual function drain pin allows v out (mosfet drain-source voltage drop) sensing without it being damaged by large voltage transients. below 5v, negligible pin leakage allows a drain low comparator to detect v out less than 2.39v (v drnl ). this, together with the gate low comparator, sets the pwrgd flag. when v out > v drncl , the drain pin is clamped at v drncl and the current flowing in r d is given by: i drn v out ? v drncl r d (1) this current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200a. this ac- celerates the fault timer pull-up when the mosfets drain-source voltage exceeds v drncl and effectively shortens the mosfet heating duration.
ltc4253/ltc4253a 17 425353afe applications information timer the operation of the timer pin is somewhat complex as it handles several key functions. a capacitor c t is used at timer to provide timing for the ltc4253/ltc4253a. four different charging and discharging modes are avail- able at timer: 1. 5a slow charge; initial timing delay. 2. (200a?+?8???i drn ) fast charge; circuit breaker delay. 3. 5a slow discharge; circuit breaker cool-off. 4. low impedance switch; resets the timer capacitor after an initial timing delay, in uvlo, in uv and in ov during initial timing and when reset is high. for initial timing delay, the 5a pull-up is used. the low impedance switch is turned off and the 5a current source is enabled when the interlock conditions are met. c t charges to 4v in a time period given by: t = 4v ? c t 5 a (2) when c t reaches v tmrh ( 4v), the low impedance switch turns on and discharges c t . a gate start-up cycle begins and both ss and gate outputs are released. circuit breaker timer operation if the sense pin detects more than 50mv drop across r s , the timer pin charges c t with (200a?+?8???i drn ). if c t charges to 4v, the gate pin pulls low and the ltc4253/ ltc4253a latch off. the ltc4253/ltc4253a remain latched off until the reset pin is momentarily pulsed high, the uv pin is momentarily pulsed low, the timer pin is momentarily discharged low by an external switch or v in dips below uvlo and is then restored. the circuit breaker timeout period is given by: t = 4v ? c t 200 a + 8?i drn (3) if v out < 5v, an internal pmos isolates drain pin leakage current and this makes i drn = 0 in equation (3). if v out is above v drncl during the circuit breaker fault period, the charging of c t is accelerated by 8 ? i drn of equation (1). intermittent overloads may exceed the 50mv threshold at sense but, if their duration is sufficiently short, timer will not reach 4v and the ltc4253/ltc4253a will not shut the external mosfet off. to handle this situation, the timer discharges c t slowly with a 5a pull-down whenever the sense voltage is less than 50mv. therefore, any intermit- tent overload with v out < 5v and an aggregate duty cycle of more than 2.5% will eventually trip the circuit breaker and shut down the ltc4253/ltc4253a. figure 4 shows the circuit breaker response time in seconds normalized to 1f. the asymmetric charging and discharging of c t is a fair gauge of mosfet heating. the normalized circuit response time is estimated by: t c t ( f) = 4 205 + 8?i drn () ?d ? 5 ? ? ? ? for d > 2.5% (4) fault duty cycle, d (%) 20 40 60 80 0 normalized response time (s/f) 10 1 0.1 0.01 100 4253 f04 t c t (f) 4 t* drn
t%o = i drn = 0a figure 4. circuit breaker response time
ltc4253/ltc4253a 18 425353afe applications information power good sequencing after the initial timer cycle, gate ramps up to turn on the external mosfet which in turn pulls drain low. when gate is within 2.8v of v in and drain is lower than v drnl , the power good sequence starts with pwrgd1 pull- ing active low. this starts off a 5a pull-up on the sqtimer pin which ramps up until it reaches the 4v threshold then pulls low. when the sqtimer pin floats, this delay t sqt is about 300s. connecting an external capacitor c sq from sqtimer to v ee modifies the delay to: t sqt = 4v ? c sq 5 a (5) pwrgd2 asserts when en2 goes high and pwrgd1 has asserted for more than one t sqt . when pwrgd2 suc- cessfully pulls low, sqtimer ramps up on another delay cycle. pwrgd3 asserts when en2 and en3 go high and pwrgd2 has asserted for more than one t sqt . all three pwrgd signals are reset in uvlo, in uv condi- tion, if reset is high or when c t charges up to 4v. in addition, pwrgd2 is reset by en2 going low. pwrgd3 is reset by en2 or en3 going low. an overvoltage condition has no effect on the pwrgd flags. a 50a current pulls each pwrgd pin high when reset. as power modules signal common are different from pwrgd , optoisolation is recommended. these three pins can sink an optodiode current. figure 17 shows an npn configuration for the pwrgd interface. a limiting base resistor should be used for each npn and the module enable input should have protection from negative bias current. soft-start soft-start is effective in limiting the inrush current during gate start-up. unduly long soft-start intervals can exceed the mosfets soa duration if powering-up into an active load. when the ss pin floats, an internal current source ramps ss from 0v to 2.2v in about 300s (0v to 1.4v in about 200s for the ltc4253a). connecting an external capacitor, c ss , from ss to ground modifies the ramp to approximate an rc response of: v ss (t) v ss 1 ? e ?t r ss c ss ? ? ? ? ? ? ? ? (6) an internal resistor divider (95k/5k for the ltc4253 and 47.5k/2.5k for the ltc4253a) scales v ss (t) down by 20 times to give the analog current limit threshold: v acl (t) = v ss (t) 20 ?v os (7) this allows the inrush current to be limited to v acl (t)/r s . the offset voltage, v os (10mv), ensures c ss is sufficiently discharged and the acl amplifier is in current limit mode before gate start-up. ss is discharged low during uvlo at v in , uv, ov, during the initial timing cycle, a latched circuit breaker fault or the reset pin going high. gate gate is pulled low to v ee under any of the following condi- tions: in uvlo, when reset pulls high, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or a latched circuit breaker fault. when gate turns on, a 50a current source charges the mosfet gate and any associated external capacitance. v in limits the gate drive to no more than 14.5v. gate-drain capacitance (c gd ) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the mosfet. a unique circuit pulls gate low with practically no usable voltage at v in and eliminates current spikes at insertion. a large external gate-source capacitor is thus unnecessary for the purpose of compensating c gd . instead, a smaller value (10nf) capacitor c c is adequate. c c also provides compensation for the analog current limit loop. gate has two comparators: the gate low comparator looks for <0.5v threshold prior to initial timing; the gate high comparator looks for <2.8v relative to v in and, together with drain low comparator, sets pwrgd1 output during gate start-up.
ltc4253/ltc4253a 19 425353afe applications information timer commences charging c t (trace 4) while the analog current limit loop maintains the fault current at 100mv/r s , which in this case is 5a (trace 2). note that the backplane voltage (trace 1) sags under load. timer pull-up is accel- erated by v out . when c t reaches 4v, gate turns off, the pwrgd signals pull high, the load current drops to zero and the backplane rings up to over 100v. the transient associated with the gate turn-off can be controlled with a snubber to reduce ringing and a transient voltage sup- pressor (such as diodes inc. smat70a) to clip off large spikes. the choice of rc for the snubber is usually done experimentally. the value of the snubber capacitor is usu- ally chosen between 10 to 100 times the mosfet c oss . the value of the snubber resistor is typically between 3 to 100. a low impedance short on one card may influence the behavior of others sharing the same backplane. the ini- tial glitch and backplane sag as seen in figure 5 trace?1, can rob charge from output capacitors on the adjacent card. when the faulty card shuts down, current flows in to refresh the capacitors. if ltc4253/ltc4253a are used by the other cards, they respond by limiting the inrush current to a value of v acl /r s . if c t is sized correctly, the capacitors will recharge long before c t times out. figure 5. output short-circuit behavior of ltc4253 sense the sense pin is monitored by the circuit breaker (cb) comparator, the analog current limit (acl) amplifier, and the fast current limit (fcl) comparator. each of these three measures the potential of sense relative to v ee . when sense exceeds 50mv, the cb comparator activates the 200a timer pull-up. at 100mv (60mv for the ltc4253a) the acl amplifier servos the mosfet current, and at 200mv the fcl comparator abruptly pulls gate low in an attempt to bring the mosfet current under control. if any of these conditions persists long enough for timer to charge c t to 4v (see equation?3), the ltc4253/ltc4253a shut down and pull gate low. if the sense pin encounters a voltage greater than v acl , the acl amplifier will servo gate downwards in an attempt to control the mosfet current. since gate overdrives the mosfet in normal operation, the acl amplifier needs time to discharge gate to the threshold of the mosfet. for a mild overload the acl amplifier can control the mosfet current, but in the event of a severe overload the current may overshoot. at sense = 200mv the fcl comparator takes over, quickly discharging the gate pin to near v ee potential. fcl then releases, and the acl amplifier takes over. all the while timer is running. the effect of fcl is to add a nonlinear response to the control loop in favor of reducing mosfet current. owing to inductive effects in the system, fcl typically overcorrects the current limit loop, and gate undershoots. a zero in the loop (resistor r c in series with the gate capacitor) helps the acl amplifier to recover. short-circuit operation circuit behavior arising from a load side low impedance short is shown in figure 5. initially the current overshoots the analog current limit level of v sense ?=?200mv (trace 2) as the gate pin works to bring v gs under control (trace?3). the overshoot glitches the backplane in the negative direc- tion and when the current is reduced to 100mv/r s , the backplane responds by glitching in the positive direction. gate 0.5ms 10v sense 0.5ms 200mv C48rtn 0.5ms 50v timer 0.5ms 5v 4253 f05 supply ring owing to current overshoot supply ring owing to mosfet turn-off onset of output short-circuit fast current limit c timer ramp latch off trace 1 trace 2 trace 3 trace 4 analog current limit
ltc4253/ltc4253a 20 425353afe mosfet selection the external mosfet switch must have adequate safe op- erating area (soa) to handle short-circuit conditions until timer times out. these considerations take precedence over dc current ratings. a mosfet with adequate soa for a given application can always handle the required current but the opposite may not be true. consult the manufacturers mosfet data sheet for safe operating area and effective transient thermal impedance curves. mosfet selection is a 3-step process by assuming the absence of soft-start capacitor. first, r s is calculated and then the time required to charge the load capacitance is determined. this timing, along with the maximum short- circuit current and maximum input voltage, defines an operating point that is checked against the mosfets soa curve. to begin a design, first specify the required load current and ioad capacitance, i l and c l . the circuit breaker cur- rent trip point (v cb /r s ) should be set to accommodate the maximum load current. note that maximum input current to a dc/dc converter is expected at v supply(min) . r s is given by: r s = v cb(min) i l(max) (8) where v cb(min) = 40mv (45mv for the ltc4253a) repre- sents the guaranteed minimum circuit breaker threshold. during the initial charging process, the ltc4253/ltc4253a may operate the mosfet in current limit, forcing (v acl ) between 80mv to 120mv (v acl is 54mv to 66mv for the ltc4253a) across r s . the minimum inrush current is given by: i inrush(min) = v acl(min) r s (9) maximum short-circuit current limit is calculated using the maximum v sense . this gives i shortcircuit(max) = v acl(max) r s (10) the timer capacitor c t must be selected based on the slowest expected charging rate; otherwise timer might time out before the load capacitor is fully charged. a value for c t is calculated based on the maximum time it takes the load capacitor to charge. that time is given by: t cl(charge) = c?v i = c l ?v supply(max) i inrush(min) (11) the maximum current flowing in the drain pin is given by: i drn(max) = v supply(max) ? v drncl r d (12) approximating a linear charging rate, i drn drops from i drn(max) to zero, the i drn component in equation (3) can be approximated with 0.5 ? i drn(max) . rearranging the equation, timer capacitor c t is given by: c t = t cl(charge) ? (200 a + 4?i drn(max) ) 4v (13) returning to equation (3), the timer period is calcu- lated and used in conjunction with v supply(max) and i shortcircuit(max) to check the soa curves of a prospec- tive mosfet. as a numerical design example for the ltc4253, consider a 30w load, which requires 1a input current at 36v. if v supply(max) = 72v and c l = 100f, r d = 1m, equation (8) gives r s ?=?40m; equation (13) gives c t = 414nf. to account for errors in r s , c t , timer current (200a), timer threshold (4v), r d , drain current multiplier and drain voltage clamp (v drncl ), the calculated value should be multiplied by 1.5, giving the nearest standard value of c t ?=?680nf. if a short-circuit occurs, a current of up to 120mv/40m?=?3a will flow in the mosfet for 6.3ms as dictated by c t = 680nf in equation (3). the mosfet must be selected based on this criterion. the irf530s can handle 100v and 3a for 10ms and is safe to use in this application. applications information
ltc4253/ltc4253a 21 425353afe computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear mosfets soa characteristics and the r ss c ss response. an overconservative but simple approach begins with the maximum circuit breaker current, given by: i cb(max) = v cb(max) r s (14) where v cb(max) is 60mv (55mv for the ltc4253a). from the soa curves of a prospective mosfet, determine the time allowed, t soa(max) . c ss is given by: c ss = t soa(max) 0.916 ? r ss for the ltc4253 c ss = t soa(max) 2.48 ? r ss for the ltc4253a (15) in the above example, 60mv/40m gives 1.5a. t soa for the irf530s is 40ms. from equation (15), c ss = 437nf. actual board evaluation showed that c ss = 100nf was ap- propriate. the ratio ( r ss ? c ss ) to t cl(charge) is a good gauge as large ratios may result in the time-out period expiring prematurely. this gauge is determined empirically with board level evaluation. summary of design flow to summarize the design flow, consider the application shown in figure 3 for the ltc4253a. it was designed for 80w and c l ?=?100f. calculate maximum load current: 80w/43v = 1.86a; allowing for 83% converter efficiency, i in(max) = 2.2a. calculate r s : from equation (8) r s = 20m. calculate i short-circuit(max) : from equation (10) i shortcircuit(max) = 3.3a. select a mosfet that can handle 3.3a at 71v: irf530s. calculate c t : from equation (13) c t = 302nf. select c t ? =? 680nf, which gives the circuit breaker time-out period t max = 5.9ms. consult mosfet soa curves: the irf530s can handle 3.3a at 100v for 8.3ms, so it is safe to use in this application. calculate c ss : using equations (14) and (15) select c ss ?=?33nf. frequency compensation the ltc4253 typical frequency compensation network for the analog current limit loop is a series r c (10) and c c connected from gate to v ee . figure 6 depicts the relationship between the compensation capacitor c c and the mosfets c iss . the line in figure 6 is used to select a starting value for c c based upon the mosfets c iss specification. optimized values for c c are shown for sev- eral popular mosfets. differences in the optimized value of c c versus the starting value are small. nevertheless, compensation values should be verified by board level short-circuit testing. as seen in figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. if this voltage avalanches the mosfet, current continues to flow through the mosfet to the output. the analog current limit loop cannot control this current flow and therefore the loop undershoots. this effect cannot be eliminated by frequency compensation. a zener diode is required to clamp the input supply voltage and prevent mosfet avalanche. figure 6. recommended compensation capacitor c c vs mosfet c iss for the ltc4253 mosfet c iss (pf) compensation capacitor c c (nf) 4253 f06 60 50 40 30 20 10 0 0 2000 4000 6000 8000 irf530 irf540 irf740 irf3710 nty100n10 applications information
ltc4253/ltc4253a 22 425353afe applications information sense resistor considerations for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4253/ ltc4253as v ee and sense pins are strongly recom- mended. the drawing in figure 7 illustrates the correct way of making connections between the ltc4253/ltc4253a and the sense resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. figure 7. making pcb connections to the sense resistor timing waveforms system power-up figure 8 details the timing waveforms for a typical power- up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. at time point 1, the supply ramps up, together with uv/ov, v out and drain. v in and the pwrgd signals follow at a slower rate as set by the v in bypass capacitor. at time point 2, v in exceeds v lko and the internal logic checks for uv > v uvhi (v uv for the ltc4253a), ov < v ovlo (v ov C v ovhst for the ltc4253a), reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os , and timer < v tmrl . when all conditions are met, initial timing starts and the timer capacitor is charged by a 5a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is quickly discharged. at time point 4, the v tmrl thresh- old is reached and the conditions of gate < v gatel , sense? ltc4253/ltc4253a 23 425353afe applications information 4253 f08 gate start-up initial timing v lko v gatel gnd C v ee or (C48rtn) C (C48v) uv/ov v in timer gate sense v out 12 3456 789 ss drain pwrgd1 ab pwrgd2 pwrgd3 sqtimer en2 en3 cd v in clears v lko , check uv > v uvhi (v uv for the ltc4253a), ov < v ovlo (v ov C v ovhst for the ltc4253a), reset < 0.8v, gate < v gatel , sense < v cb 44t7 os and timer < v tmrl timer clears v tmrl , check gate < v gatel , sense < v cb "/%44t7 os v sqtmrh 5a 5a v sqtmrh v ih v ih v tmrh v acl v cb v tmrl t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 5a 5a 50a 50a v drncl v drnl v in C v gateh ?"t* drn figure 8. system power-up timing (all waveforms are referenced to v ee )
ltc4253/ltc4253a 24 425353afe applications information live insertion with short pin control of uv/ov in the example shown in figure 9, power is delivered through long connector pins whereas the uv/ov divider makes contact through a short pin. this ensures the power connections are firmly established before the ltc4253/ ltc4253a are activated. at time point 1, the power pins make contact and v in ramps through v lko . at time point?2, the uv/ov divider makes contact and its voltage exceeds figure 9. power-up timing with a short pin (all waveforms are referenced to vee) gate start-up initial timing v uvhi v lko v gatel v sqtmrh v sqtmrl gnd C v ee or (C48rtn) C (C48v) uv/ov v in timer gate sense uv clears v uvhi (v uv for the ltc4253a), check ov < v ovhi (v ov for the ltc4253a), reset < 0.8v, gate < v gatel , sense < v cb 44t7 os and timer < v tmrl v out 12 3456 78 9 timer clears v tmrl , check gate < v gatel , sense < v cb "/%44t7 os ss drain pwrgd1 a b pwrgd2 pwrgd3 sqtimer en2 en3 c d 5a 5a v sqtmrh 4253 f09 v sqtmrl v tmrh v acl v cb v tmrl t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 5a 5a 50a 50a 50a v drncl v drnl v in C v gateh ?"t* drn
ltc4253/ltc4253a 25 425353afe applications information v uvhi (v uv for the ltc4253a). in addition, the internal logic checks for ov < v ovhi (v ov for the ltc4253a), reset < 0.8v, gate < v gatel , sense < v cb , ss < 20 ? v os and timer? v lko to start. in an undervoltage lockout condition, both uv and ov comparators are held off. when v in exits undervoltage lockout, the uv and ov comparators are enabled. overvoltage timing during normal operation, if the ov pin exceeds v ovhi (v ov for the ltc4253a) as shown at time point?1 of fig- ure 11, the timer and pwrgd status are unaffected; ss and gate pull down; load disconnects. at time point 2, ov recovers and drops below the v ovlo (v ov C v ovhst for the ltc4253a) threshold; gate start-up begins. if the overvoltage glitch is long enough to deplete the load capacitor, time points?4 through 7 may occur. circuit breaker timing in figure 12a, the timer capacitor charges at 200a if the sense pin exceeds v cb but v drn is less than 5v. if the sense pin returns below v cb before timer reaches the v tmrh threshold, timer is discharged by 5a. in figure? 12b, when timer exceeds v tmrh , gate pulls down immediately and the chip shuts down. in figure?12c, multiple momentary faults cause the timer capacitor to integrate and reach v tmrh followed by gate pull down and the chip shuts down. during chip shutdown, the ltc4253/ltc4253a latch timer high with a 5a pull-up current source.
ltc4253/ltc4253a 26 425353afe applications information 50a v sqtmrl uv clears v uvhi (v uv for the ltc4253a), check ov condition, reset < 0.8v, gate < v gatel , sense < v cb 44t7 os and timer < v tmrl timer clears v tmrl , check gate < v gatel , sense < v cb "/%44t7 os uv timer gate sense ss drain pwrgd1 pwrgd2 pwrgd3 sqtimer en2 en3 12 3456789abcd 4253 f10 initial timing gate start-up t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 5a uv drops below v uvlo (v uv C v uvhst for the ltc4253a). gate, ss and timer are pulled down, pwrgd releases v uvlo v gatel v uvhi v acl v sqtmrh v sqtmrl v cb 5a 5a 50a v sqtmrh v drncl v drnl v in C v gateh 50a ?"t* drn v tmrh v tmrl 5a figure 10. undervoltage timing (all waveforms are referenced to v ee )
ltc4253/ltc4253a 27 425353afe applications information v acl v cb v in C v gateh ov timer gate sense ss 123456789 gate start-up 4253 f11 ov drops below v ovlo (v ov C v ovhst for the ltc4253a), check gate < v gatel , sense < v cb "/%44t7 os ov overshoots v ovhi (v ov for the ltc4253a). gate and ss are pulled down, pwrgd signals and timer are unaffected v ovhi v ovlo v tmrh v gatel t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 50a 5a ?"t* drn cb fault cb fault cb fault cb fault 12 1 2 12 34 timer gate sense v out ss drain pwrgd1 timer gate sense v out ss drain pwrgd1 timer gate sense v out ss drain pwrgd1 4253 f12 cb times-out cb times-out v tmrh v acl v cb v acl v cb 5a 5a v drncl ?"t* drn ?"t* drn v tmrh v acl v cb v drncl ?"t* drn v tmrh figure 11. overvoltage timing (all waveforms are referenced to v ee ) figure 12. circuit breaker timing behavior (all waveforms are referenced to v ee ) (12a) momentary circuit breaker fault (12b) circuit breaker time-out (12c) multiple circuit breaker fault
ltc4253/ltc4253a 28 425353afe applications information resetting a fault latch a latched circuit breaker fault of the ltc4253/ltc4253a has the benefit of a long cooling time. the latched fault can be reset by pulsing the reset pin high until the timer pin is pulled below v tmrl (1v) as shown in figure 13b. after the reset pulse, ss and gate ramp up without an initial timing cycle provided the interlock conditions are satisfied. alternative methods of reset include using an external switch to pulse the uv pin below v uvlo (v uv C v uvhst for the ltc4253a) or the v in pin below (v lko C v lkh ). pulling the timer pin below v tmrl and the ss pin to 0v then simultaneously releasing them also achieves a reset. an initial timing cycle is generated for reset by pulsing the uv pin or v in pin, while no initial timing cycle is generated for reset by pulsing of the timer and ss pins. using reset as an on/off switch the asynchronous reset pin can be used as an on/off function to cut off supply to the external power modules or loads controlled by the ltc4253/ltc4253a. pulling reset high will pull gate, ss, timer and sqtimer low and the pwrgd signal high. the supply is fully cut off if the reset pulse is maintained wide enough to fully discharge the gate and ss pins. as long as reset is high, gate, ss, timer and sqtimer are strapped to v ee and the supply is cut off. when reset is released, if the ltc4253/ltc4253a are in uvlo, uv, ov or v sense > v cb , turn-on is delayed until the interlock conditions are met before recovering as described in the operation, interlock conditions section. if not, the gate pin will ramp up in a soft start cycle without going through an initial cycle as in figure 13c. analog current limit and fast current limit in figure 14a, when sense exceeds v acl , gate is regulated by the analog current limit amplifier loop. when sense drops below v acl , gate is allowed to pull up. in figure 14b, when a severe fault occurs, sense exceeds v fcl and gate immediately pulls down until the analog current amplifier establishes control. if the severe fault causes v out to exceed v drncl , the drain pin is clamped at v drncl . i drn flows into the drain pin and is multiplied by?8. this extra cur- rent is added to the timer pull-up current of 200a. this accelerated timer current of (200a?+?8???i drn ) produces a shorter circuit breaker fault delay. careful selection of c t , r d and mosfet helps prevent soa damage in a low impedance fault condition. soft-start i f the ss pin is not connected, this pin defaults to a linear voltage ramp, from 0v to 2.2v in about 300s (0v to 1.4v in about 200s for the ltc4253a) at gate start-up, as shown in figure 15a. if a soft-start capacitor, c ss , is con- nected to this ss pin, the soft-start response is modified from a linear ramp to an rc response (equation?6), as shown in figure 15b. this feature allows load current to slowly ramp-up at gate start-up. soft-start is initiated at time point 3 by a timer transition from v tmrh to v tmrl (time points 1 and 2), by the ov pin falling below the v ovlo (v ov C v ovhst for the ltc4253a) threshold after an ov condition or by the reset pin falling < 0.8v after a reset condition. when the ss pin is below 0.2v, the analog cur- rent limit amplifier keeps gate low. above 0.2v, gate is released and 50a ramps up the compensation network and gate capacitance at time point 4. meanwhile, the ss pin voltage continues to ramp up. when gate reaches the mosfets threshold, the mosfet begins to conduct. due to the mosfets high g m , the mosfet current quickly reaches the soft-start control value of v acl (t) (equation?7). at time point?6, the gate voltage is controlled by the current limit amplifier. the soft-start control voltage reaches the circuit breaker voltage, v cb at time point?7 and the circuit breaker timer activates. as the load capacitor nears full charge, load current begins to decline below v acl (t). the current limit loop shuts off and gate releases at time point?8. at time point?9, sense voltage falls below v cb and timer deactivates. large values of c ss can cause premature circuit breaker time-out as v acl (t) may marginally exceed the v cb potential during the circuit breaker delay. the load capacitor is un- able to achieve full charge in one gate start-up cycle. a more serious side effect of a large c ss value is that soa duration may be exceeded during soft-start into a low impedance load. a soft-start voltage below v cb will not activate the circuit breaker timer.
ltc4253/ltc4253a 29 425353afe applications information figure 13. reset functions (all waveforms are referenced to v ee ) (13a) reset forcing start-up without initial timer cycle (13b) reset of the ltc4253/ltc4253as latched fault (13c) reset as an on/off switch reset pulse width must fully discharge timer 123456789 latched timer reset by reset pulling high reset < v il , check uvlo, uv, ov condition, gate < v gatel , sense < v cb 44t7 os and timer < v tmrl timer gate sense reset ss drain pwrgd1 uv/ov v tmrh v ih v il v acl v cb v tmrl v gatel v lko v uvhi t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 5a 50a 50a 5a 50a v drncl v drnl v in C v gateh ?"t* drn reset pulse width must fully discharge gate and ss 123456789 4253 f13 reset < v il , check uvlo, uv, ov condition, v sense < v cb timer gate sense reset ss drain pwrgd1 uv/ov v ih v il v acl v cb v tmrl v gatel v lko v uvhi t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 50a 5a 50a v drncl v drnl v in C v gateh ?"t* drn 123 4 567 8 reset < v il , check uvlo, uv, ov condition, gate < v gatel , sense < v cb 44t7 os and timer < v tmrl timer gate sense reset ss drain pwrgd1 v in v in v in uv/ov v il v acl v cb v tmrl v gatel v lko t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 50a 5a 50a v drncl v drnl v in C v gateh ?"t* drn v uvhi
ltc4253/ltc4253a 30 425353afe applications information figure 14. current limit behavior (all waveforms are referenced to v ee ) (14a) analog current limit fault (14b) fast current limit fault figure 15. soft-start timing (all waveforms are referenced to v ee ) (15a) without external c ss (15b) with external c ss 12 12 34 timer gate sense v out ss drain pwrgd1 timer gate sense v out drain pwrgd1 4253 f14 cb times-out v tmrh v acl v cb v acl v fcl v cb 5a ?"t* drn ?"t* drn v drncl v tmrh 12 34 5 6 7 7a 8 9 10 11 end of initial timing cycle 12 3 4 5 6 7 8 9 10 11 end of initial timing cycle 4253 f15 timer gate sense ss drain pwrgd1 v tmrh v acl v cb v tmrl v tmrh v tmrl v gs(th) v gs(th) t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 50a 50a v drncl v drnl v in C v gateh ?"t* drn timer gate sense ss drain pwrgd1 v acl v cb t 7 acl + v os ) t 7 cb + v os ) t7 os 5a 50a 50a 50a v drncl v drnl v in C v gateh ?"t* drn
ltc4253/ltc4253a 31 425353afe applications information power limit circuit breaker figure 16 shows the ltc4253a in a power limit circuit breaking application. the sense pin is modulated by board voltage v supply . the d1 zener voltage, v z , is set to be the same as the lowest operating voltage, v supply(min) ?=?43v. if the goal is to have the high supply operating voltage, v supply(max) = 71v give the same power as available at v supply(min) , then resistors r3 and r4 are selected by: r4 r3 = v cb v supply(max) (16) if r4 is 22, then r3 is 31.6k. the peak circuit breaker power limit is: power(max) = v supply(min) + v supply(max) () 2 4?v supply(min) ?v supply(max) ?power at v supply(min) = 1.064 ? power at v supply(min) (17) when v supply = 0.5 ? (v supply(min) + v supply(max) ) = 57v figure 16. power limit circuit breaker application r6 5.6k r5 5.6k d1 bzv85c43 r7 5.6k pwrgd1 v in v in v ee ltc4253a power module 1 pwrgd2 pwrgd3 en3 en2 ov uv reset drain ss gate sqtimer sense timer en power module 2 en power module 3 en r in 2.5k 15k(1/4w)/6 r3 31.6k en3 4253 f16 en2 r c 10 r d 1m r s 0.02 q1 irf530s v in c c 10nf r4 22 c t 0.68f c1 10nf c sq 0.1f c ss 33nf r8 power module 1 output power module 2 output v in r9 + c3 0.1f c2 100f c in 1f r2 392k 1% r1 30.1k 1% ? ? ?? ? reset (long pin) C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin) d in ?? ddz13b* *diodes, inc. ? moc207 ?? recommended for harsh environments.
ltc4253/ltc4253a 32 425353afe gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) applications information the peak power at the fault current limit occurs at the supply overvoltage threshold. the fault current limited power is: power(fault) = v supply () r s ?v acl ? (v supply ? v z )? r4 r3 ? ? ? ? ? ? (18) circuit breaker with foldback current limit figure 17 shows the ltc4253a in a foldback current limit application. when v out is shorted to the C48v rtn supply, current flows through resistors r3 and r4. this results in a voltage drop across r4 and a corresponding reduction in voltage drop across the sense resistor, r s , as the acl amplifier servos the sense voltage between the sense and v ee pins to about 60mv. the short-circuit current through rs reduces as the v out voltage increases during an output short-circuit condition. without foldback current limiting resistor r4, the current is limited to 3a during analog current limit. with r4, the short-circuit current is limited to 0.5a when v out is shorted to 71v. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) w 45 s 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc4253/ltc4253a 33 425353afe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 2/11 obsoleted ltc4253a revised application drawings replaced shunt regulator section 2 12, 14, 15, 21, 25 to 32, 34 14 e 3/12 not recommended for new designs 1 (revision history begins at rev d)
ltc4253/ltc4253a 34 425353afe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2002 lt 0312 rev e ? printed in usa related parts typical application part number description comments lt1640ah/lt1640al negative high voltage hot swap controllers in so-8 negative high voltage supplies from C10v to C80v lt1641-1/lt1641-2 positive high voltage hot swap controllers in so-8 supplies from 9v to 80v, autoretry/latched off LTC1642A fault protected hot swap controller 3v to 16.5v, overvoltage protection up to 33v lt4250 C48v hot swap controller active current limiting, supplies from C20v to C80v ltc4251/ltc4251-1/ ltc4251-2 C48v hot swap controllers in sot-23 fast active current limiting, supplies from C15v ltc4252-1/ltc4252-2 ltc4252a-1/ltc4252a-2 C48v hot swap controllers in ms8/ms10 fast active current limiting, supplies from C15v, drain accelerated response, 1% accurate uv/ov thresholds figure 17. C48v/2.5a application with foldback current limiting and transistor enabled sequencing without feedback r6 100k r5 100k r7 100k pwrgd1 v in en2 en3 v in v ee ltc4253a power module 1 pwrgd2 pwrgd3 ov uv reset drain ss gate sqtimer sense timer en power module 2 en power module 3 en r in 10k 20k(1/4w)/2 4253 f17 r c 10 r3 38.3k r d 3.3m r s 0.02 q1 irf530s v out c c 10nf r4 22 c t 1f c1 10nf r8 47k c sq 0.1f c ss 33nf + c3 0.1f c2 100f c in 1f r2 392k 1% r1 30.1k 1% ? ? ? reset (long pin) C 48v rtn (short pin) C 48v rtn (long pin) C 48v (long pin) *diodes, inc. ? fmmt493 ?? recommended for harsh environments. d in ?? ddz13b*

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